1. Field of the Invention
The present invention relates to a variable-resistance memory device employing memory cells each including an access transistor and a data storage element, which is connected in series to the access transistor to serve as a data storage element with a resistance changing in accordance with a voltage applied to the data storage element, and relates to a method for operating the variable-resistance memory device.
2. Description of the Related Art
There has been already known a variable-resistance memory device employing memory cells each including a data storage element which has a resistance changing due to injection of conductive ions into an insulation film of the data storage element or due to extraction of such ions from the insulation film. For more information on this variable-resistance memory device, the reader is suggested to refer to a document such as K. Aratani, etc., “A Novel Resistance Memory with High Scalability and Nanosecond Switching,” Technical Digest IEDM 2007, pp. 783-786 (hereinafter referred to as Non-patent Document 1).
The data storage element has a laminated structure constructed by creating a conductive-ion supplying layer and the insulation film cited above between two electrodes of the data storage element.
Every of the memory cell employs a data storage element and an access transistor which are connected to each other in series between first and second wires drivable in an active matrix driving operation. Since the memory cell employs the access transistor (T) and a variable-resistance resistor (R) serving as the data storage element, the memory cell is referred to as a 1T1R-type memory cell.
The variable-resistance memory device employing 1T1R-type memory cells is referred to as a ReRAM (Resistance Random Access Memory).
As described in the document such as Non-patent Document 1, the resistance of a data storage element employed in the ReRAM is used to indicate a state in which data has been stored in the data storage element or a state in which data has been erased from the data storage element. That is to say, the resistance of a data storage element indicates the value of data stored in the data storage element. A data write operation to store data in a data storage element and a data erase operation to erase data from a data storage element can be carried out by applying a pulse having a small width of the order of some ns (nanoseconds) to the data storage element. Thus, since the ReRAM is an NVM (non-volatile memory) capable of operating at as high a speed as a RAM (Random Access Memory), the ReRAM draws much attention.
In the present invention, the data erase operation is defined as an operation carried out to store inverted data in the data storage element employed in the memory cell. The inverted data is data opposite to data stored in the data storage element by carrying out the data write operation. In this specification of the present invention, in case it is not necessary to distinguish the data write operation and the data erase operation from each other, both the data write and data erase operations are referred to as a data update operation which is a generic technical term for them. In the following description, the aforementioned pulse applied to a memory cell to carry out an update operation is also referred to as an update pulse.
In order for the ReRAM to serve as a substitute for a flash memory which is the contemporary NVM of the FG (Floating Gate)_NAND type, however, it is necessary for the ReRAM to surmount several barriers. One of the barriers is a requirement for a good control characteristic of the execution of a high-speed verify operation.
A verify operation is a read operation carried out after application of an update pulse of an update operation in order to read out data from the data storage element in an attempt to verify that the update operation has been carried out normally.
As a method for carrying out a verify operation on a memory cell at a high speed, there is known a method in which residual electric charge remaining on a bit line BL connected to the memory cell after application of an update pulse is discharged through the memory cell in an electrical discharge process, and a voltage change occurring on the bit line BL as a result of the electrical discharge process is detected by making use of a voltage sensor such as a sense amplifier. For more information on this method for carrying out a verify operation at a high speed, the reader is suggested to refer to a document such as Japanese Patent Laid-Open No. 2007-133930 (hereinafter referred to as Patent Document 1).
In accordance with the verify operation method disclosed in Patent Document 1, a verify operation is carried out immediately after application of an update pulse without waiting for a waiting time to lapse. Since there is no waiting time required between the application of an update pulse and the execution of the verify operation, the verify operation can be completed in a short period of time. For this reason, in the following description, the verify operation is referred to as a direct verify operation which means a verify operation carried out immediately after application of an update pulse without waiting for a waiting time to lapse.